The x3550  M2 ships with registered double data rate III (DDR-3) memory and provides Active Memory features, including advanced Chipkill memory protection (optionally), for up to 16X better error correction than standard ECC memory. In addition to offering better performance than DDR-2 or fully-buffered memory, DDR-3 memory also uses less energy. DDR-2 memory already offered up to 37% lower energy use than fully buffered memory. Now, a generation later, DDR-3 memory is even more efficient, using 22% less energy than DDR-2 memory.
The x3550  M2 supports up to 128GB of memory (when the 8GB memory is released)  in sixteen DIMM slots. Redesign in the architecture of the Xeon 5500 Series processors bring radical changes in the way memory works in these servers. For example, the Xeon 5500 Series Processor integrates the memory controller inside the processor, resulting in two memory controllers in a 2-socket system. Each memory controller has three memory channels. Depending on the type of memory, population of memory, and processor model, the memory may be clocked at 1333MHz, 1066MHz or 800MHz.  Note: If only one processor is installed, only the first eight DIMM slots can be used. Adding a second processor not only doubles the amount of memory available for use, but also doubles the number of memory controllers, thus doubling the system memory bandwidth. If you add a second  processor, but no additional memory for the second processor, the second processor has to access the memory from the first processor "remotely," resulting in longer latencies and lower performance. The latency to access remote memory is almost 75% higher than local memory access. So, the goal should be to always populate both processors with memory.
The X55xx models support up to 1333MHz memory clock speed, , while the E55xx-and-up and L55xx-and-up models support up to 1066MHz clock speed, , and the E550x models support 800MHz clock speed.. Using 1333MHz memory (where supported) versus 1066MHz offers up to 9% better performance, while 1066MHz memory produces up to 28% better performance than 800MHz memory.
Xeon 5550 series processors access memory with almost 50% lower latency than the previous generation 5400 series processors. That can result in faster processing of latency-sensitive workloads.  This new processor design comes with some trade-offs in memory capacity, performance, and cost: For example, greater memory capacity comes with lower memory speed. Alternatively, it is possible to achieve the same memory capacity at lower cost but at a lower memory speed.  Regardless of memory speed, the Xeon 5500 platform represents a significant improvement in memory bandwidth over the previous Xeon 5400 platform. At 1333MHz, the improvement is  almost 500% over the previous generation. This huge improvement is mainly due to the dual integrated memory controllers and faster DDR-3 1333MHz memory. Throughput at 800MHz is 25 gigabytes per second (GBps); at 1066MHz it's 32GBps; and at 1333MHz it's 35GBps. This improvement translates into improved application performance and scalability.  Memory interleaving refers to how physical memory is interleaved across the physical DIMMs. A balanced system provides the best interleaving. A Xeon 5500 processor-based system is balanced when all memory channels on a socket have the same amount of memory.  A memory rank is simply a segment of memory that is addressed by a specific address bit.  DIMMs typically have 1, 2 or 4 memory ranks, as indicated by their size designation.
• A typical memory DIMM description is 2GB 4Rx8 DIMM • The 4R designator is the rank count for this particular DIMM (R for rank = 4)
• The x8 designator is the data width of the rank It is important to ensure that DIMMs with appropriate number of ranks are populated in each channel for optimal performance. Whenever possible, it is recommended to use dual-rank DIMMs in the system. Dual-rank DIMMs offer better interleaving and hence better performance than single-rank DIMMs. For instance, a system populated with six 2GB dual-rank DIMMs outperforms a system populated with six 2GB single-rank DIMMs by 7% for SPECjbb2005. Dualrank DIMMs are also better than quad-rank DIMMs because quad-rank DIMMs will cause the memory speed to be down-clocked.  Another important guideline is to populate equivalent ranks per channel. For instance, mixing one single-rank DIMM and one dual-rank DIMM in a channel should be avoided.  Note: It is important to ensure that all three memory channels in each processor are populated.  The relative memory bandwidth decreases as the number of channels populated decreases. This is because the bandwidth of all the memory channels is utilized to support the capability of the processor. So, as the channels are decreased, the burden to support the requisite bandwidth is increased on the remaining channels, causing them to become a bottleneck. For increased availability, the x3550 M2 offers an additional (but mutually exclusive) level of IBM Active Memory protection: online memory mirroring.  Memory mirroring works much like disk mirroring. The total memory is divided into two channels.  Data is written concurrently to both channels. If a DIMM fails in one of the DIMMs in the primary channel, it is instantly disabled and the mirrored (backup) memory in the other channel becomes active (primary) until the failing DIMM is replaced. One-half of total memory is available for use with mirroring enabled. (Note: Due to the double writes to memory, performance is affected.)  Mirroring is handled at the hardware level; no operating system support is required.  DDR-3 memory is available in 1GB, 2GB, 4GB and 8GB DIMMs (not out yet). DIMMs are installed individually (not in pairs).

The following rules apply to single-rank and dual-rank DDR3 DIMM speed as it
relates to the number of DIMMs in a channel:

– When you install 1 DIMM per channel, the memory runs at 1333 MHz
– When you install 2 DIMMs per channel, the memory runs at 1066 MHz
– When you install 3 DIMMs per channel, the memory runs at 800 MHz
– All channels in a server run at the fastest common frequency.
– Mixing registered and unbuffered DIMMs is not supported

A minimum of one DIMM must be installed for each microprocessor. For example, you must install a minimum of two DIMMs if the server has two microprocessors. However, to improve system performance, install a minimum of three DIMMs for each microprocessor.  The maximum operating speed of the server is determined by the slowest DIMM in the server.

The server requires at least one DIMM per microprocessor. The server comes with a minimum of two 1 GB DIMMs, installed in connectors 3 and 6. (Connectors 3 and 6 are the farthest connectors for channels 0 and 1 of microprocessor 1.) When you install additional DIMMs, install them in the order shown in Table 7, to maintain performance.         Important: If you have configured the server to use memory mirroring, do not use the order in Table 7; go to "Memory mirroring" and use the installation order shown there.